module board(
    input   clk_i,
    input   rst,
    input  [23:0] io_sw,

    output led_ca ,
    output led_cb ,
    output led_cc ,
    output led_cd ,
    output led_ce ,
    output led_cf ,
    output led_cg ,
    output led_dp ,
    output [7:0]  led_en,
    output [23:0] io_led
    
    );
    
    wire we;
    wire clk;
    wire rst_n = ~rst;

    wire [31:0] inst, pc;
    wire [31:0] rd, adr, wdin;

    wire debug_wb_ena;
    wire debug_wb_have_inst;
    wire [4:0]  debug_wb_reg;
    wire [31:0] debug_wb_pc;
    wire [31:0] debug_wb_value;

    cpuclk UCLK(
        .clk_in1    (clk_i),
        .clk_out1   (clk)
    );

    pipeline_CPU U_pipeline_CPU (
        .clk            (clk),
        .rst_n          (rst_n),
        .irom_inst      (inst),     
        .dram_rd        (rd),       
        .irom_pc        (pc),      
        .dram_adr       (adr),      
        .dram_wdin      (wdin),     
        .dram_we        (we),      
        .debug_wb_have_inst (debug_wb_have_inst),
        .debug_wb_pc        (debug_wb_pc),
        .debug_wb_ena       (debug_wb_ena),
        .debug_wb_reg       (debug_wb_reg),
        .debug_wb_value     (debug_wb_value)
    );
    

    IROM U_IROM(
        .pc         (pc),
        .inst       (inst)
    );

    assign ram_clk = !clk;

    DRAM U_DRAM(
        .clk        (ram_clk),
        .adr        (adr),
        .wdin       (wdin),
        .dram_we    (we),
        .rd         (rd),
        
        .io_sw     (io_sw),
        .io_led    (io_led)
    );

    led_display_ctrl U_led_display_ctrl(
        .clk        (clk),
        .rst_n      (rst_n),
        .cal_result (io_led),
        .led_en     (led_en),
        .led_ca     (led_ca),
        .led_cb     (led_cb),
        .led_cc     (led_cc),
        .led_cd     (led_cd),
        .led_ce     (led_ce),
        .led_cf     (led_cf),
        .led_cg     (led_cg),
        .led_dp     (led_dp)
    );


endmodule
